IBIS Macromodel Task Group Meeting date: 19 February 2019 Members (asterisk for those attending): ANSYS: Dan Dvorscak * Curtis Clark Cadence Design Systems: * Ambrish Varma Brad Brim Kumar Keshavan Ken Willis eASIC: David Banas GlobalFoundries: Steve Parker IBM Luis Armenta Trevor Timpane Intel: Michael Mirmak Keysight Technologies: Fangyi Rao * Radek Biernacki Ming Yan Stephen Slater Maziar Farahmand Mentor, A Siemens Business: John Angulo * Arpad Muranyi Micron Technology: Randy Wolff * Justin Butterfield SiSoft (Mathworks): Walter Katz Mike LaBonte SPISim: * Wei-hsing Huang Synopsys: Rita Horner Kevin Li Teraspeed Consulting Group: Scott McMorrow Teraspeed Labs: * Bob Ross The meeting was led by Arpad Muranyi. Curtis Clark took the minutes. -------------------------------------------------------------------------------- Opens: - None. ------------- Review of ARs: - Randy to investigate if/why/how a clock waveform input might be used. - In progress. - Michael M. to investigate if/why/how a clock waveform input might be used. - In progress. - Michael M. to check with IP experts on whether DC_Offset is useful for Tx. - In progress. - Mike L. to reach out to FEC presentation authors for more information. - Not yet done. -------------------------- Call for patent disclosure: - None. ------------------------- Review of Meeting Minutes: Arpad asked for any comments or corrections to the minutes of the February 12 meeting. Bob moved to approve the minutes. Justin seconded the motion. There were no objections. ------------- New Discussion: No one had anything new to discuss for the current agenda topics: - DDR5 related issues. - Complex C_comp modeling Arpad asked for additional discussion or motions to untable any other topics. There were none. - Bob: Motion to adjourn. - Curtis: Second. - Arpad: Thank you all for joining. ------------- Next meeting: 26 February 2019 12:00pm PT ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives